Forum Discussion
New ContributorWhy are signals rx_is_locktodata and rx_is_locktoref always at 0?
Hi,
As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.
I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
Thanks for your update. Just to check with you if rx_analogreset = 0 in your observation? If rx_analogreset = 0 but rx_is_locktoref stays 0, you might need to double check again on your refclk to CDR. If normal case, after analog reset released, CDR will attempt to achieve lock to the local refclk to CDR and rx_is_locktoref = 1 when lock-to-ref. Then, without valid signal supplied to RX, the CDR rx_is_locktoref and rx_is_locktodata will toggle between 0 and 1 when attempting to achieve lock-to-data mode.
It is recommend to check on the following as well:
1. Is the CLKUSR pin connected to free-running oscillator on-board with frequency 100MHz - 125MHz? This is to ensure successful power up calibration of the transceiver to ensure normal functionality.
2. Is the refclk to CDR connected to free-running oscillator on-board? This clock need to be stable as well before device power up to ensure successful power up calibration.
By the way, just to check with you on the follwoing:
1. If you build a design similar to the A10 working design from scratch, with all parameters similar to A10 design, is the design still failing in C10GX device?
2. Did you manage to get any XCVR design up and running in your C10GX device before?
3. Are you using any C10GX devkit?
4. Can you try with this design for C10GX FPGA Devkit from Design Store https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/ to see if it work?
Please let me know if there is any concern. Thank you.
- Длаза
Hi!
I checked my rx_analogreset. It is matched figure 150 of user guide "Intel Arria10 Transceiver PHY..". If there is a problem with refclk, then why is your project working?
1.CLKUSR is connected to external generator 100MHz. Should i specify somewhere its settings (assignments, device and pin options, constrain)?
2. refclk is connected to CDR by analogy with your project. Refclk is connected to Si5338, but this generator is programmable. First loaded project configures Si5338, then reconfig fpga, then i loaded my project ( or native1g).
About Cyclone10GX.
I have devkit cyclone10GX. There I did my project with Custom Native_PHY (Standart PCS, data rate = 4000Mbps, refclk=625MHz XCVR = 4ch). Its worked. But when transferring from devkit to my hardware with project stops working. I change settings from refclk==625MHz to refclk==156.25MHz.
