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Длаза's avatar
Длаза
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Why are signals rx_is_locktodata and rx_is_locktoref always at 0?

Hi, guys! I created project with 4channel transceiver. But, I can't working because "Transceiver Reset Controller" the controller always holds "rx_ready" at 0. My project is full compilied. Wh...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.

    I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.

    Please let me know if there is any concern. Thank you.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. Regarding the C10GX, as I understand it, you have had a test design running on C10GX devkit. However, when you transfer this design to your own C10GX board, the design does not work.


Based on the observation that C10GX devkit is working fine, this could help to narrow down to your board. Please correct me if I am wrong, in your C10GX board, the ATX PLL has no issue achieving lock. And the TX ready is also High. The issue is only with the RX CDR unable to achieve lock to refclk or data.


To facilitate the debugging on the C10GX, can you try the following:


1. Build a simple one channel Native PHY design with data rate 1.25Gbps + 156.25MHz and serial loopback enabled using the latest Q20.3Pro. Leave other settings in Native PHY default.


2. Test this design on C10GX devkit to see if it works (ATX lock, TX ready, RX CDR LTD). Monitor with SignalTap.


3. If #2 is working, change the refclk and XCVR pinouts to test with your own C10GX board. No configuration change is required because it is already 156.25MHz.


4. If #3 is not working, you should further investigate into your board to see if there is any anomaly ie XCVR power supplies, refclk frequencies and etc.


5. To ensure successful power up calibration, you should ensure the CLKUSR, ATX PLL refclk and CDR refclk are all free-running and stable prior to power up FPGA. These clocks should be directly connected to on-board free-running oscillators.


6. If the above still not working, you can try again by configuring Native PHY to enable the rx_set_locktodata and rx_set_locktoref ports. This would allow you to manually control the CDR lock mode. Try forcing the CDR to LTR mode to see if it works.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin