What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

Hi JohnT,

Issue is the same when we try accessing the flash device through software through PCIe (no JTAG Master). We can read the flash ID and what we think is flash memory but we can't write to it. This basically led us to debug the IP via JTAG Master then find that page write also doesn't work whenever PCIe hard IP is present. Suggestions?

r/joel

Hi JohnT,

Yes I can send a QAR file. I don't see an option to attach file here... email?

Thanks!

Direct message sent. Thanks!

Hi John,

Here's our code:

// NEW for testing Config SPI Flash FPGA IP core

#define REG_FLASH_IP_CSR 0x10000000 // offset from PCIe BAR2 base address

// the following are offsets from REG_FLASH_IP_CSR

#define FLASH_CONTROL_REG 0x00 // Control register bit8 1=4byte add,keep bit0 at 1, 0 = disable outputs

#define FLASH_OP_PROTO_SET 0x10 // Operating Protocol Setting Register

#define FLASH_RD_INST_REG 0x14 // Read Instruction Register

#define FLASH_WR_INST_REG 0x18 // Write Instruction Register

#define FLASH_CMD_SET 0x1C //31-21 reserved|20-16 #dummy cycles|15-12 #w/r data bytes|11 0=wr 1=rd|10-8 #address bytes|7-0 opcode|

#define FLASH_CMD_START 0x20 //write 1 to start

#define FLASH_ADDRESS 0x24 // address for the operation

#define FLASH_WR_DATA0 0x28 // first 4 bytes write data

#define FLASH_WR_DATA1 0x2C // last 4 bytes write data

#define FLASH_RD_DATA0 0x30 // first 4 bytes read data

#define FLASH_RD_DATA1 0x34 // last 4 bytes read data

#define FLASH_IP_MEM 0x8000000

#define FPGA_ONCHIP_MEM 0x100000

void PCIJTAG2_API FlashIpStuff(void)

{

U32 DataRead;

WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x0); // normal extended mode for all operations

// Read Device IDs

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000489F); // opcode 9F, no address, write bit 11 set = read, 4 bytes, 0 dummy cycles

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);

printf("\nDeviceID = 0x%x\n",DataRead);

// Clear sector protect by writing the status Register

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x00001001); // opcode 01, write bit 0 = write

WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_DATA0, 0x20); // bit 5 for bottom start - all protect bits cleared

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

// Enter 4 byte addressing

FlashSetWriteEnable();

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000000B7); // write opcode b7 - no address or data bytes

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CONTROL_REG,0x00000101); // Tell Flash IP we are using 4-byte addressing

FlashEraseSector(0xB000000); // sector 11 64KB sectors

WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_INST_REG,0x00007012); // 70h status read, 12h 4-byte page program opcode

WritePciJtag(FLASH_IP_MEM+0xB00000,0xFACEFACE);

CheckStatus();

WritePciJtag(REG_FLASH_IP_CSR+FLASH_RD_INST_REG,0x00000013); // 0 dummy cycles 13h 4-byte read opcode

DataRead = ReadPciJtag(FLASH_IP_MEM+0xB00000);

printf("\nDataRead = 0x%x\n",DataRead);

}

void FlashSetWriteEnable(void)

{

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET, 0x00000006);// write opcode 6

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

}

void FlashEraseSector(U32 address)

{

// Erase using 4 byte address

FlashSetWriteEnable();

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000004D8); // write opcode D8 sector erase - 4 address bytes

WritePciJtag(REG_FLASH_IP_CSR+FLASH_ADDRESS,address); // address

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

}

void CheckStatus(void)

{

U32 DataRead,i=0;

do

{

Sleep(5);

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x0004870);//status read of 4 bytes of data

WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command

DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);

}while((DataRead != 0x81818181)&& (i < 500));

}

Output:

DeviceID = 0x1021bb20

DataRead = 0xffffffff

Hi,

The procedure that was run is PCIJTAG2_API FlashIpStuff. It's the same sequence used on System Console using TCL script. We didn't try using SignalTap because the same sequence is being executed on TCL and SW and all works on both except for Page Program on SW. The Avalon bus is assumed to be OK since we can read the flash ID and read from the flash device. The IP handles the EPCQL interface, so what part should we use SignalTap on?

Hi,

Have you try the solution that I provided?