What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

Hi,

I bbserved that you are using standard SPI protocol which the command, address and data is used for standard and not extended mode.

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x0); // normal extended mode for all operations"

For extended SPI mode, you will need to set it to

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x22220); // normal extended mode for all operations"

Please be aware that this setting is not suitable for sector erase but only for read and write operation that you plan to use extended SPI mode.

The write instruction that you are using is for extended SPI mode.

"WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_INST_REG,0x00007012); // 70h status read, 12h 4-byte page program opcode"

So you will need to make the changes so that you are running the write correctly to opcode 02h if you would like to use normal SPI mode.

Opcode 13h to performed read. May I know if you are able to use 03h opcode to performed read?

WritePciJtag(REG_FLASH_IP_CSR+FLASH_RD_INST_REG,0x00000013); // 0 dummy cycles 13h 4-byte read opcode

If you plan to use extended SPI mode then you will need to use Opcode EBh,