Forum Discussion
JBayl
Occasional Contributor
Occasional ContributorWhat's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?
My setup is: Cyclone 10 GX Development Board FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master. Testing this setup through System Console I was able ...
JohnT_Altera
Regular Contributor
Regular ContributorHi,
May I know if you are able to send me your Quartus design? I am suspecting that the issue is due to the timing constraint.
JBaylOccasional Contributor
Occasional ContributorHi JohnT,
Yes I can send a QAR file. I don't see an option to attach file here... email?
Thanks!
