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JBayl's avatar
JBayl
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6 years ago

What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

My setup is: Cyclone 10 GX Development Board FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master. Testing this setup through System Console I was able ...
JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi John,

I have forwarded the JIC to SW. What have you done and can you forward your QAR so I can study and compare while I wait for SW to evaluate your JIC?

Thanks!