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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

My setup is: Cyclone 10 GX Development Board FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master. Testing this setup through System Console I was able ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I would recommend you to only connect it to single Avalon-MM master to the Generic Serial Flash IP. May I know if there is any issue if you are connecting only to the PCIe hard IP?

  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi JohnT,

    Issue is the same when we try accessing the flash device through software through PCIe (no JTAG Master). We can read the flash ID and what we think is flash memory but we can't write to it. This basically led us to debug the IP via JTAG Master then find that page write also doesn't work whenever PCIe hard IP is present. Suggestions?

    r/joel