Forum Discussion

JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

My setup is: Cyclone 10 GX Development Board FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master. Testing this setup through System Console I was able ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for providing the code but what I observed is the code for each procedure.

May I know which procedure do you run? May I know if you are running the same procedure when you used JTAG Master? Are you able to use SignalTap to see if the command is send correctly into the Generic Serial Flash Interface IP?

JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi,

The procedure that was run is PCIJTAG2_API FlashIpStuff. It's the same sequence used on System Console using TCL script. We didn't try using SignalTap because the same sequence is being executed on TCL and SW and all works on both except for Page Program on SW. The Avalon bus is assumed to be OK since we can read the flash ID and read from the flash device. The IP handles the EPCQL interface, so what part should we use SignalTap on?