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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

My setup is: Cyclone 10 GX Development Board FPGA Design contains the Generic Serial Flash IP, PCIe hard ip, and the JTAG to Avalon Master. Testing this setup through System Console I was able ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

May I know if you are able to send me your Quartus design? I am suspecting that the issue is due to the timing constraint.

  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi JohnT,

    Yes I can send a QAR file. I don't see an option to attach file here... email?

    Thanks!