Video Clocked output and VGA

well, did you take a look here http://www.altera.com/literature/an/an427.pdf ?

remember that in de2 sdram controller works fine @50 MHz, not over. Other sdram controllers work up to 100Mhz only in newest stratix IV fbga..

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How about the components? is it enough with just adding framebuffer?

should i add frameread component? but framebuffer does have output pin on it

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OK, i found a documentation altera_video_image_processing.pdf (http://www.bitec.ltd.uk/altera_video_image_processing.pdf) (page19) that said the vip framebuffer is built with its own reader to read memory, so isuppose there is no need to add a frame reader.

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well, did you take a look here http://www.altera.com/literature/an/an427.pdf ?

remember that in de2 sdram controller works fine @50 MHz, not over. Other sdram controllers work up to 100Mhz only in newest stratix IV fbga..

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thanks for the documentation..

actually i use the 108MHz clock because i refer it from the de2_70_tv design example. (im using de2-70 board).. but in that design it use a custom verilog design sdram controller with 2 wr and 2 read port. Mybe the 108MHz clock wont work on sdram controller IP provided .. I'll try change it to 50Mhz and see what it does.

how about the 27Mhz clock for test pattern gen & VGA..

i think it should work rite. because without the framebuffer & sdram added. they work just fine with 27Mhz clock.

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Originally Posted by phate http://www.alteraforum.com/forum/../proweb/buttons/viewpost.gif (http://www.alteraforum.com/forum/showthread.php?p=88728#post88728)

well, did you take a look here http://www.altera.com/literature/an/an427.pdf ?

remember that in de2 sdram controller works fine @50 MHz, not over. Other sdram controllers work up to 100Mhz only in newest stratix IV fbga..

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thanks for the documentation..

actually i use the 108MHz clock because i refer it from the de2_70_tv design example. (im using de2-70 board).. but in that design it use a custom verilog design sdram controller with 2 wr and 2 read port. Mybe the 108MHz clock wont work on sdram controller IP provided .. I'll try change it to 50Mhz and see what it does.

how about the 27Mhz clock for test pattern gen & VGA..

i think it should work rite. because without the framebuffer & sdram added. they work just fine with 27Mhz clock.

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ive change the clock for sdram to 50MHz.

good improvement. now i can see a correct colors. thanks

These are what i get:

https://www.alteraforum.com/forum/attachment.php?attachmentid=2401

https://www.alteraforum.com/forum/attachment.php?attachmentid=2402

unfortunately it is not as it supposed to be. the input is color bar test from test_pattern_gen module.and the output is supposed to be like this.

https://www.alteraforum.com/forum/attachment.php?attachmentid=2403

any suggestion for improvement?

hi phate..i found this post of yours in another thread..

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I have encountered many problems in order to understand how to correctly set parameter for bursting using the frame buffer (or deinterlacer).

in an427, they (altera) set a port width of 128 because of the half data rate controller (wich quadruples the DDR sdram witdh). So, 64 bits-witdh are for the write fifo, and 64 for the read fifo.

So, why burst size target is set to 32?

Now, i am trying to use a similar system in my vip, but instead of a DDR I have only a SDR with a data width of 16 bits,and the ip of the controller Altera provides works fine only with a clock of 50Mhz.

I've empirically found out that wit 64-32-16-32-16 bits, it seems to work properly.

But honestly, I didn't understand WHY this settings are correct.

Could any one help me to understand why?

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have you got the system running with framebuffer added using that setting u said?

yep.

using the test pattern generator all systems works fine.

The problem is when I try to use the CVI (with the ADV on board), I am not able to have a good image on output, maybe i use wrong fifos settings for cvi and cvo.

I tougth that without using buffers in the deinterlacer, the system would have work properly, but it seems i was wrong. I know I am wrong, but i don't know exactly WHERE.

Anyway, the board you are using has different components from mine (in example, i am SURE i have an SDR sdram, maybe your board ha a DDR sdram?) so maybe my settings would not work properly on your project.

Another consideration about your project: what reolution do you wanto to achieve as output VGA?

you should configure clovked video output with correct timings and pixel clocks in order to work properly, and i Think that @ 60Hz 640*480 27Mhz is not the correct pixel clock... ;)

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Another consideration about your project: what reolution do you wanto to achieve as output VGA?

you should configure clovked video output with correct timings and pixel clocks in order to work properly, and i Think that @ 60Hz 640*480 27Mhz is not the correct pixel clock...

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yep im also using vga 640x480..sorry but in the previous post i didnt rename the clock but the input is actually 25MHz generated from PLL outside sopc.

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I've empirically found out that wit 64-32-16-32-16 bits, it seems to work properly

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by this do you mean

avalon mm masterport width : 64bits

write only master interface fifo depth : 32bits

write only master interface burst target : 16bitsread only master interface fifo depth : 32bits

read only master interface burst target : 16bits

How about the

-align read/write burst

-framedrop

-frame-repetition

should i tick it?

and what should be the correct packets buffered per frame

& maximum packet length

well,

if in your system RAM runs @100Mhz, it should be right.

TESTpat-> fbuff-> CVO

in order to meet bandwitdth requirements, i set 5bit per color plane (SDR sdram in DE2 has a data-bit length of 16bit. so 5bit per pixel implies 15 bits, 8 bits per pixel implies 24 bits).

In your system, i'll try to use 5bit per color plane in test pattern gen.

and parallel color planes.

for CVO which are your settings?

So, if the components for de2-70 are similar, for the frame buffer,i think that my settings could work for you.

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for CVO which are your settings?

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here is my setting for cvo

https://www.alteraforum.com/forum/attachment.php?attachmentid=2419

however using only patternGen & cvo i get a correct output if the color is 8bit per plane..maybe because it is not connected to SDRAM. My SDRAM chip each also has 16bits datawidth.

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So, if the components for de2-70 are similar, for the frame buffer,i think that my settings could work for you.

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i will try your setting for framebuffer and see

thanks