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well, did you take a look here
http://www.altera.com/literature/an/an427.pdf ?
remember that in de2 sdram controller works fine @50 MHz, not over. Other sdram controllers work up to 100Mhz only in newest stratix IV fbga..
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thanks for the documentation..
actually i use the 108MHz clock because i refer it from the de2_70_tv design example. (im using de2-70 board).. but in that design it use a custom verilog design sdram controller with 2 wr and 2 read port. Mybe the 108MHz clock wont work on sdram controller IP provided .. I'll try change it to 50Mhz and see what it does.
how about the 27Mhz clock for test pattern gen & VGA..
i think it should work rite. because without the framebuffer & sdram added. they work just fine with 27Mhz clock.
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