Unable to run example design for 25G ethernet IP for startix device(1SGO85HN2F4312VG)

Hello everyone,

I am trying to run simulation for the 25g Ethernet IP for startix fpga with fpga number 1SGO85HN2F4312VG. As per @https://www.intel.co.jp/content/www/jp/ja/programmable/documentation/gkr1505413442088.html#ezc1519265402640 I am running the simulation on modelsim. I am facing some issues in running the script.

The error message that I recieve is:

# do run_vsim.do
# ** Warning: (vlib-34) Library already exists at "work".
# basic_avl_tb_top
# C:\intelFPGA_pro\19.3\quartus
# ../ex_25g/sim
# false
# false
# bit_32
# -t fs
# work work_lib altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver fourteennm_ver fourteennm_ct1_ver altera lpm sgate altera_mf altera_lnsim fourteennm fourteennm_ct1
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5c Lib Mapping Utility 2017.01 Jan 23 2017
# vmap work ./libraries/work/
# Modifying modelsim.ini
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5c Lib Mapping Utility 2017.01 Jan 23 2017
# vmap work_lib ./libraries/work/
# Modifying modelsim.ini
# altera_common_sv_packages 1 altera_xcvr_native_s10_htile_1921 1 alt_e25s10_1930 1 altera_xcvr_atx_pll_s10_htile_191 1 altera_xcvr_reset_control_s10_191 1 altera_merlin_master_translator_191 1 altera_merlin_slave_translator_191 1 altera_merlin_master_agent_191 1 altera_merlin_slave_agent_191 1 altera_avalon_sc_fifo_191 1 altera_merlin_router_191 1 altera_merlin_traffic_limiter_191 1 alt_hiconnect_sc_fifo_191 1 altera_merlin_burst_adapter_191 1 altera_merlin_demultiplexer_191 1 altera_merlin_multiplexer_191 1 altera_mm_interconnect_191 1 alt_e25s10_avmm_fabric_multichannel_1930 1 ex_25g 1
# altera_common_sv_packages altera_xcvr_native_s10_htile_1921 alt_e25s10_1930 altera_xcvr_atx_pll_s10_htile_191 altera_xcvr_reset_control_s10_191 altera_merlin_master_translator_191 altera_merlin_slave_translator_191 altera_merlin_master_agent_191 altera_merlin_slave_agent_191 altera_avalon_sc_fifo_191 altera_merlin_router_191 altera_merlin_traffic_limiter_191 alt_hiconnect_sc_fifo_191 altera_merlin_burst_adapter_191 altera_merlin_demultiplexer_191 altera_merlin_multiplexer_191 altera_mm_interconnect_191 alt_e25s10_avmm_fabric_multichannel_1930 ex_25g
# ** Error: couldn't create error file for command: permission denied
# Error in macro ./../ex_25g/sim/mentor/msim_setup.tcl line 233
# couldn't create error file for command: permission denied
# while executing
# "error [FixExecError $msg]"
# (procedure "vmap" line 29)
# invoked from within
# "vmap $library ./libraries/$library/"
# ("foreach" body line 3)
# invoked from within
# "foreach library $libraries {
# ensure_lib ./libraries/$library/
# vmap $library ./libraries/$library/
# lappend logical_libraries $library
# }"

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The second method that I tried is to copy all the *.vhd,*.v,*.sv files in a seperate folder and compile them in modelsim in work library only (and of course changing the library in the internal files).

In this process, I face an error and mdoelsim exits with code 211 along with this info in vstf file:

# Current time Fri Apr 23 11:05:48 2021
# ModelSim - Intel FPGA Edition Stack Trace
# Program = vsim
# Id = "10.5c"
# Version = "2017.01"
# Date = "Jan 23 2017"
# Platform = win32pe
# Signature = 5e7f9b833961c34eb19f3225262e3a77
# 0 0x71046b2e: 'fdopen + 0x844' in 'c:\windows\system32\msvcr120.dll'
# 1 0x710b4aaf: 'vsnprintf_l + 0x81' in 'c:\windows\system32\msvcr120.dll'
# 2 0x710b4a29: 'vsnprintf + 0x16' in 'c:\windows\system32\msvcr120.dll'
# 3 0x01299c54: '<unknown (@0x1299c54)>'
# 4 0x004c13d2: '<unknown (@0x4c13d2)>'
# End of Stack Trace

Kindly help me.

Regards

Abhinav Behl