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Abhinav_behl's avatar
Abhinav_behl
Icon for New Contributor rankNew Contributor
4 years ago

Unable to run example design for 25G ethernet IP for startix device(1SGO85HN2F4312VG)

Hello everyone, I am trying to run simulation for the 25g Ethernet IP for startix fpga with fpga number 1SGO85HN2F4312VG. As per @https://www.intel.co.jp/content/www/jp/ja/programmable/documentati...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi


I was running at Linux by using v19.3 and using the same script as you, everything looks fine. Today, I tested it in my window system with v20.4 (v19.3 is not available in my setup), and it is working fine as well. Since v19.3 was an older version, I would suggest you move to v20.4 or later, and if you still encounter the problem, we can debug from there.


Regards -SK


Abhinav_behl's avatar
Abhinav_behl
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4 years ago

Hi @SengKok_L_Intel ,

As per your suggestion, I have Quartus 20.4 installed on my laptop. When I try to run the script from Cygwin I am getting the same issue. I am attaching the screenshot for it. I am using intel FPGA ModelSim version 2019.2

To remove these error I breakdown the script and compiled in ModelSim. I was able to run the "com" command (which is for compiling files in the correct order(as per the script)). But when I try to run the "elab" command I am getting the same error as with the previous versions. I am attaching the transcript for the same( after running "elab").

Let me know if you require any other files.

Kindly help me I am stuck with this problem for a very long.

Regards

Abhinav Behl