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Abhinav_behl's avatar
Abhinav_behl
Icon for New Contributor rankNew Contributor
4 years ago

Unable to run example design for 25G ethernet IP for startix device(1SGO85HN2F4312VG)

Hello everyone, I am trying to run simulation for the 25g Ethernet IP for startix fpga with fpga number 1SGO85HN2F4312VG. As per @https://www.intel.co.jp/content/www/jp/ja/programmable/documentati...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


What Quartus version that you are using? Could you please double-check if there is any permission (write enable) concern on your system?


Regards -SK Lim


  • Abhinav_behl's avatar
    Abhinav_behl
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    4 years ago

    Hi @SengKok_L_Intel,

    Thanks for your prompt reply,

    I am using Quartus 19.3. And yes I have double-checked write permissions, I am running it on windows and every permission is given to all files.

    Yesterday I also tried one more thing to open the ModelSim GUI and add files manually and then compile using compile auto-generate option in ModelSim. In compilation also get errors. Apart from that when I try to run the simulation for top-level design, Modelsim exits with code 211 and the same message is printed in the .vstf file(to check vstf file I am told by ModelSim). For this step, I have attached the transcript file.

    Please help me!

    Regards

    Abhinav Behl