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Altera_Forum
Honored Contributor
Honored Contributortiming questions -false path for the experts
Hi,
I have a design that has value in it that define the code behavior, let call them: config_reg table_of_vaule 1. because of the nature of those things, they are deep in the design. 2. those values are being configured using 25Mhz clock 3. values are used using a 100Mhz clock. I run a set_flase_path : set_false_path -from [get_keepers {config_reg}] set_false_path -to[get_keepers {config_reg}] make sure than when I write and read I hold the values10 clocks, make sure it sticks. Another code run on a different 100Mhz, used config_reg(0) to branch. Assuming values at config_reg are stable does the set_flase_path has any damaging effect? @100Mhz if(a=1 and config_reg(0)) then ... what about that: @100Mhz if(a=1 and config_reg(sel)) then ... where sel and a are 100Mhx values with NO false_path on them. thanks20 Replies
Altera_ForumI read your first post and re-read it but you are not explaining the clocking scheme around (a).
I understand you are clocking the register conf_reg with 25MHz. But what about register (a)? is it on 25MHz or 100MHz? From your statemet "if a=1 and conf_reg(0)" I know it is on clock 100MHz thereafter- Altera_Forum
@100Mhz
if(a=1 and config_reg(sel)) then ... "a" and "sel" are at 100Mhz, and config_reg is 25Mhz, granting not to change. - Altera_Forum--- Quote Start --- @100Mhz if(a=1 and config_reg(sel)) then ... "a" and "sel" are at 100Mhz, and config_reg is 25Mhz, granting not to change. --- Quote End --- Ok so reg(a) is clocked by 100MHz, so is reg(sel) but conf_reg is clocked by 25MHz. path 1) The path from conf_reg can be made false, but not the one (to) conf_reg, and path 2) provided the path on clock 100MHz from (a) to next register is given enough time to settle since (a) output could change anytime an may violate clock 100MHz. If you are not sure insert two registers on clock 100MHz just before (a) register.
- Altera_Forum
The other option is to use en1 on reg(a) and en2 on next register and control delay of sampling between en1 & en2
- Altera_Forum
reg "a" will sample "config_reg" once at 100Mhz in one of the steps on the state machine....
values from register "a" are not set to false path.... process(clk100mhz) beginif (rising_edge(clk100mhz)) then if (sig_from_another_100mhz_process='1') then a<=config_reg; a_was_set<='1'; else a_was_set<='0'; end if; if (a_was_set='1') then b<=a; end if; end if; end process; b and a should be able to hold the correct value of config_Reg, assuming config_reg does ***not*** changes - Altera_Forum--- Quote Start --- The other option is to use en1 on reg(a) and en2 on next register and control delay of sampling between en1 & en2 --- Quote End --- just to correct myself. if conf_reg is constant then there is no problem. you can set false path from it an ignore my other notes
- Altera_Forum--- Quote Start --- just to correct myself. if conf_reg is constant then there is no problem. you can set false path from it an ignore my other notes --- Quote End --- is not define as a "constant" in vhdl, however.... it will not change...
- Altera_Forum--- Quote Start --- is not define as a "constant" in vhdl, however.... it will not change... --- Quote End --- so it is set early well before design starts using it even if (a) samples it from start the design is idle. That is ok
- Altera_Forum
thank you.
what about : a<=config_reg(sel); where a,sel are 100Mhz ? - Altera_Forum--- Quote Start --- thank you. what about : a<=config_reg(sel); where a,sel are 100Mhz ? --- Quote End --- sel being generated in clk 100MHz domain is ok.
