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Altera_Forum's avatar
Altera_Forum
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8 years ago

timing questions -false path for the experts

Hi, I have a design that has value in it that define the code behavior, let call them: config_reg table_of_vaule 1. because of the nature of those things, they are deep in the design. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

reg "a" will sample "config_reg" once at 100Mhz in one of the steps on the state machine....

values from register "a" are not set to false path....

process(clk100mhz)

beginif (rising_edge(clk100mhz)) then

if (sig_from_another_100mhz_process='1') then

a<=config_reg;

a_was_set<='1';

else

a_was_set<='0';

end if;

if (a_was_set='1') then

b<=a;

end if;

end if;

end process;

b and a should be able to hold the correct value of config_Reg, assuming config_reg does ***not*** changes