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Altera_Forum's avatar
Altera_Forum
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8 years ago

timing questions -false path for the experts

Hi, I have a design that has value in it that define the code behavior, let call them: config_reg table_of_vaule 1. because of the nature of those things, they are deep in the design. ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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is not define as a "constant" in vhdl, however.... it will not change...

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so it is set early well before design starts using it even if (a) samples it from start the design is idle. That is ok