Stratix 10 Transceiver MGTREFCLK in LVDS

Hi,

As I understand it, you have some inquiries related to the S10 XCVR refclk IO standard. For your information, the supported refclk IO standards for L/H Tile are CML, Differential LVPECL, LVDS, and HCSL. Therefore, there should be no problem to use LVDS as IO standard.

By default, Quartus will assign 100 Ohm OCT for refclk. You would not need to do any specific assignment for this. You can double check at Fitter report after compilation.

Sorry as I am not very clear with the following, would you mind to help further elaborating:

"If you compile a new design with transceivers and then just back annotate the pins, the MGTREFCLK pins get set in CLM."

Please let me know if there is any concern. Thank you.

Hi,

Please see my responses to your latest inquiries as following:

1. Please, give me the link to the document about the supported refclk IO standards for L/H Tile.

[CP] You may refer to the S10 datasheet at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf. Look for "L-Tile Reference Clock Specifications" and "H-Tile Reference Clock Specifications" sections.

Please, give me the link to the document about Quartus assigning 100 Ohm OCT for refclk by default.

[CP] You would need to run a compilation with Quartus to check on this.

You say that, if there is no termination on the board, I should just assign LVDS I/O standard in the Assignment Editor, and don't assign any internal termination at all?

[CP] You can verify if the 100 Ohm OCT is turned ON from the Fitter report after compilation. You can create a simple test design with Native PHY to try out.

Please let me know if there is any concern. Thank you.

Hi,

Thanks for your update. Please share with me your test design to further look into. By the way, just to check if your XCVR refclks are connected to XCVR instances ie Native PHY?

Thank you.

Hi,

Thanks for your update and sharing of the test design. For your information, in the Fitter report, specific to transceiver refclks, the "tristate_off" = OCT is enabled. You can refer to the "Dedicated Reference Clock Pin Termination" section in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for further details.

The following are the mapping of the termination value:

1. TRISTATE_OFF: Internal termination enabled and on-chip biasing circuitry enabled

2. TRISTATE_ON: Internal termination tri-stated. Off-chip termination and biasing circuitry must be implemented

In other words, your Fitter report is showing the expected result where OCT is enabled for XCVR refclk.

Please let me know if there is any concern. Thank you.

Hi,

Please see my responses as following:

So, for the XCVR_S10_REFCLK that I want to be LVDS, I should just assign them as LVDS in the Assignment Editor, and don't assign any termination, correct?

[CP] Yes, your understanding is correct. Note that you should always double check again in the Fitter report after compilation.

For all the other LVDS signals which have no external termination, I must assign them as LVDS in the Assignment Editor and also assign the Internal Termination as Differential, correct?

[CP] This is applicable to GPIOs. Again, please double check again in Fitter report to ensure the termination is there.

Hi,

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.