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Mircea's avatar
Mircea
Icon for New Contributor rankNew Contributor
4 years ago

Stratix 10 Transceiver MGTREFCLK in LVDS

Hello, I have a question regarding the reference clocks for the Stratix 10 transceivers: Is it OK to set their I/O standard LVDS with Differential Input Termination? The Stratix 10 Dev Kit has ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


As I understand it, you have some inquiries related to the S10 XCVR refclk IO standard. For your information, the supported refclk IO standards for L/H Tile are CML, Differential LVPECL, LVDS, and HCSL. Therefore, there should be no problem to use LVDS as IO standard.


By default, Quartus will assign 100 Ohm OCT for refclk. You would not need to do any specific assignment for this. You can double check at Fitter report after compilation.


Sorry as I am not very clear with the following, would you mind to help further elaborating:


"If you compile a new design with transceivers and then just back annotate the pins, the MGTREFCLK pins get set in CLM."


Please let me know if there is any concern. Thank you.



  • Mircea's avatar
    Mircea
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi,

    Please, give me the link to the document about the supported refclk IO standards for L/H Tile.

    Please, give me the link to the document about Quartus assigning 100 Ohm OCT for refclk by default.

    You say that, if there is no termination on the board, I should just assign LVDS I/O standard in the Assignment Editor, and don't assign any internal termination at all?

    Thank you.