Stratix 10 Transceiver MGTREFCLK in LVDS

Hi,

Thanks for your update and sharing of the test design. For your information, in the Fitter report, specific to transceiver refclks, the "tristate_off" = OCT is enabled. You can refer to the "Dedicated Reference Clock Pin Termination" section in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for further details.

The following are the mapping of the termination value:

1. TRISTATE_OFF: Internal termination enabled and on-chip biasing circuitry enabled

2. TRISTATE_ON: Internal termination tri-stated. Off-chip termination and biasing circuitry must be implemented

In other words, your Fitter report is showing the expected result where OCT is enabled for XCVR refclk.

Please let me know if there is any concern. Thank you.