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Mircea's avatar
Mircea
Icon for New Contributor rankNew Contributor
4 years ago

Stratix 10 Transceiver MGTREFCLK in LVDS

Hello, I have a question regarding the reference clocks for the Stratix 10 transceivers: Is it OK to set their I/O standard LVDS with Differential Input Termination? The Stratix 10 Dev Kit has ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Please see my responses as following:


So, for the XCVR_S10_REFCLK that I want to be LVDS, I should just assign them as LVDS in the Assignment Editor, and don't assign any termination, correct?

[CP] Yes, your understanding is correct. Note that you should always double check again in the Fitter report after compilation.


For all the other LVDS signals which have no external termination, I must assign them as LVDS in the Assignment Editor and also assign the Internal Termination as Differential, correct?

[CP] This is applicable to GPIOs. Again, please double check again in Fitter report to ensure the termination is there.