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rtldeseng's avatar
rtldeseng
Icon for New Contributor rankNew Contributor
9 days ago

Stratix 10 fPLL is cascade source mode doesn't lock

Hello everyone.

I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode.

In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal.

After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1.

Is there any known issue about fPLL is cascade source mode?

Any suggestions about how to overcome this issue are welcomed.

Other Ips
Transceiver

1 Reply

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    48 minutes ago

    Hi,

    Can you please provide few details about your design?

    1) What is the input clock frequency and source of it?

    2) What is the output frequency that you are trying to achieve?

    3) Is the create_clock constraint applied for the input clock at the top level?

     

    Few design implementation checks would be:

    1) You must recalibrate the PLL when the reference clock is available.

    2) Clock on OSC_CLK_1 signal is used for calibration of the fPLL and it must be stable. Is it true for your case?

     

    It would be easier to debug if you can provide a reference design to reproduce the issue.

     

    Regards