Stratix 10 emif DDR timing failure

Hi Adzim,

Thank you for your help. But I cannot open the project since I'm using Quartus Pro 20.1. Can you please share the project in an older version？

Best regards,

Shu

Hi Adzim,

In the IP configurations panel the user clock frequency can only be set to a quarter of the memory clock frequency, so does it mean I should change the memory clock frequency? But in the way I'm wondering:

1. In the user manual of the Stratix 10 board it says the 133.3333MHz PLL reference clock is generated by the hardware device Silicon Lab Si5338 on the board. If I change the memory clock frequency I have to change the PLL reference clock frequency at the same time. Is there a way to reconfigure the device to generate a different frequency than 133.3333MHz?

2. If I change the memory clock frequency should I also change the Mem timing parameters?

Thanks,

Shu

Hi Adzim,

Perhaps I didn't explain my questions clearly, but in your last reply you said I can make a change on the user clock frequency. But in the configuration panel it only allows the user clock frequency to be quarter the memory clock frequency. Then how can I make change to the user clock frequency while keeping the memory clock frequency at 1200MHz? Or I have to change the memory clock frequency at the same time?

And the PLL reference frequency is also limited in these options. If I set memory clock frequency to 1200MHz then I cannot choose 133.33MHz as PLL reference frequency. Is there a way to reconfigure the Si5338 hardware to get a different frequency?

Thanks,

Shu

Hi Adzim,

Sorry for my late reply. Now I've set the memory clock frequency to 1200MHz and PLL reference clock frequency to 150MHz.

Then in the clock controller I set CLK1 (which is what I'm using for this emif) to 150MHz, but then I see that the emif is not working: both the local_cal_success and local_cal_fail port are low, and I cannot get access to the memory.

I tried to reset the emif by pressing the nreset button (S20) on the board but the emif cannot get reset. In the qsys file I've connected the local_reset_combiner and the emif like what is done in your example, and the local_reset_req port is connected to the nreset button. Is there anything wrong with my design?

Thank you,

Shu Wang

Hi Adzim,

Yes, I've regenerated the IP and compiled the design after I changed the memory clock frequency and PLL reference clock frequency.

The 1066.667MHz example design is working correctly in my design. I've validated it by writing to a certain address and reading it with HPS. So I think the pin connections should be fine.

But since I want to change the user clock frequency (which is fixed at 1/4 memory clock frequency) and use the user clock in my FPGA program, it would be helpful if you can help me figure out why the 1200MHz design is not working.

Thanks,

Shu

Hi Adzim,

I've checked the pin locations and it was same with the 1066.67MHz design.

When I'm using 300MHz PLL clock frequency it works with the default setting (actual reference clock frequency is 133.3333MHz), but after I change the reference clock frequency to 300MHz in the clock controller it stops working. And I have the same problem when I set PLL clock frequency to 150MHz.

I've regenerated the IP files before compiling and I've checked the clock frequency in the generated files. It doesn't seem to be the problem of improperly generated files.

Thanks,

Shu