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shuw
New Contributor
New ContributorStratix 10 emif DDR timing failure
I'm using the 16GB FPGA DDR4 Memory on the Stratix 10 SX SoC Development Kit. When I'm configuring the emif for the FPGA Memory I cannot find the correct timing parameters for the given memory in the...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Shu,
Regarding to the Clock rate of user logic, the clock can only be set to Quarter rate when using the DDR4 interface.
The PLL reference frequency is limited to the options.
You can only choose from the options.
You can reconfigure the Clock in the Clock Controller application.
You need to install the app first.
You need to identify which clock that has been used and then you can change it.
Please let me know if you face any trouble in doing it.
Regards,
Adzim
