Forum Discussion
New ContributorStratix 10 emif DDR timing failure
Regular ContributorHi Shu,
I think your configuration should be fine.
There is a possibility to cause that when comparing the HPS DDR and FPGA DDR.
The HPS DDR has a circuitry that already been assigned for the EMIF.
But the FPGA DDR can be used any bank that available.
You can make a change on the user clock frequency but it's needs to be in it's range.
Then you have to regenerate the EMIF IP and compile your design.
Please let me know if you have further question.
Thanks,
Adzim
shuwHi Adzim,
In the IP configurations panel the user clock frequency can only be set to a quarter of the memory clock frequency, so does it mean I should change the memory clock frequency? But in the way I'm wondering:
1. In the user manual of the Stratix 10 board it says the 133.3333MHz PLL reference clock is generated by the hardware device Silicon Lab Si5338 on the board. If I change the memory clock frequency I have to change the PLL reference clock frequency at the same time. Is there a way to reconfigure the device to generate a different frequency than 133.3333MHz?
2. If I change the memory clock frequency should I also change the Mem timing parameters?
Thanks,
Shu
