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shuw's avatar
shuw
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4 years ago

Stratix 10 emif DDR timing failure

I'm using the 16GB FPGA DDR4 Memory on the Stratix 10 SX SoC Development Kit. When I'm configuring the emif for the FPGA Memory I cannot find the correct timing parameters for the given memory in the...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Shu,


Thank you for your confirmation.

Make sure that the pin locations that have been used in the 1200MHz design is same with the 1066.67MHz.

Is it working if you used 300MHz PLL clock frequency?


Regards,

Adzim


shuw's avatar
shuw
Icon for New Contributor rankNew Contributor
4 years ago

Hi Adzim,

I've checked the pin locations and it was same with the 1066.67MHz design.

When I'm using 300MHz PLL clock frequency it works with the default setting (actual reference clock frequency is 133.3333MHz), but after I change the reference clock frequency to 300MHz in the clock controller it stops working. And I have the same problem when I set PLL clock frequency to 150MHz.

I've regenerated the IP files before compiling and I've checked the clock frequency in the generated files. It doesn't seem to be the problem of improperly generated files.

Thanks,

Shu