Stratix 10 emif DDR timing failure

Hi Adzim,

Sorry for my late reply. Now I've set the memory clock frequency to 1200MHz and PLL reference clock frequency to 150MHz.

Then in the clock controller I set CLK1 (which is what I'm using for this emif) to 150MHz, but then I see that the emif is not working: both the local_cal_success and local_cal_fail port are low, and I cannot get access to the memory.

I tried to reset the emif by pressing the nreset button (S20) on the board but the emif cannot get reset. In the qsys file I've connected the local_reset_combiner and the emif like what is done in your example, and the local_reset_req port is connected to the nreset button. Is there anything wrong with my design?

Thank you,

Shu Wang