Forum Discussion
New ContributorStratix 10 emif DDR timing failure
Regular ContributorHi Shu,
I just review the example design that I've shared before.
I think that the Memory Clock Frequency should be 1200MHz.
You can select the PLL reference clock frequency or you can choose to use the recommended PLL reference clock frequency.
The Mem Timing is based on the Speed Bin and Memory Clock Frequency.
But I think 1200MHz should be the right one.
Regards,
Adzim
New ContributorHi Adzim,
Perhaps I didn't explain my questions clearly, but in your last reply you said I can make a change on the user clock frequency. But in the configuration panel it only allows the user clock frequency to be quarter the memory clock frequency. Then how can I make change to the user clock frequency while keeping the memory clock frequency at 1200MHz? Or I have to change the memory clock frequency at the same time?
And the PLL reference frequency is also limited in these options. If I set memory clock frequency to 1200MHz then I cannot choose 133.33MHz as PLL reference frequency. Is there a way to reconfigure the Si5338 hardware to get a different frequency?
Thanks,
Shu
