Forum Discussion
New ContributorStratix 10 emif DDR timing failure
Regular ContributorHi Shu,
I have created an EMIF example design with the specified memory timing parameter.
I have shared the project in .qar file.
I hope that you will be able to compile it and work on it.
Regards,
Adzim
New ContributorHi Adzim,
Thank you for your help. But I cannot open the project since I'm using Quartus Pro 20.1. Can you please share the project in an older version？
Best regards,
Shu
- AdzimZM_Altera
Hi Shu,
I'm sorry that I was not aware you were using the Quartus Pro v20.1.
I've created the project in Quartus Pro v20.1 and shared in .qar file.
Regards,
Adzim
- shuw
Hi Adzim,
Thank you for your help. Now I'm using the configurations as in your example project. But since my FPGA program is in a diffrerent clock field and has an AXI full interface, I connect my AXI master to the avalon_mm_ctrl port through a avalon clock crossing bridge as shown in the figure. Is that a good choice? If not, what else can I do to cross the different clock field between emif and my FPGA program?
I'm having this question because I'm comparing the read and write speed between the 4GB HPS DDR and the 16GB FPGA DDR on the Stratix 10 board. And the results show that the speed is lower when using FPGA memory. So I'm suspecting the interconnect between AXI and avalon and the clock crossing bridge may increase the total latency. Is that possible?
Thank you,
Shu
- shuw
Hi Adzim,
As a supplement to my previous question, what is the frequency of the user clock in the emif IP? Am I able to change it? If I could change it perhaps I can use this clock in my FPGA program.
Best regards,
Shu
