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shuw's avatar
shuw
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4 years ago

Stratix 10 emif DDR timing failure

I'm using the 16GB FPGA DDR4 Memory on the Stratix 10 SX SoC Development Kit. When I'm configuring the emif for the FPGA Memory I cannot find the correct timing parameters for the given memory in the...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Shu,

Just for confirmation, have you regenerated the IP and compiled the design after some changes on the EMIF IP?

If you already did, then you can check the pin connection as the Fitter might assigns the pins to different locations.

May I know if the 1066.667MHz example design is working on your board?

The design that I shared to you before.

Regards,

Adzim

  • shuw's avatar
    shuw
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Adzim,

    Yes, I've regenerated the IP and compiled the design after I changed the memory clock frequency and PLL reference clock frequency.

    The 1066.667MHz example design is working correctly in my design. I've validated it by writing to a certain address and reading it with HPS. So I think the pin connections should be fine.

    But since I want to change the user clock frequency (which is fixed at 1/4 memory clock frequency) and use the user clock in my FPGA program, it would be helpful if you can help me figure out why the 1200MHz design is not working.

    Thanks,

    Shu