Single Avalon-MM Master to Muliple Avalon-MM Slaves

Everything in Qsys including creating components, and connecting ports can be done in the command line if that's what you are worried about.

It ain't pretty, but:

Thanks Ted- I'll give it a try. Altera certainly does not make this simple task very easy (which is ironic since the whole point of qsys is to make things easier).

I wouldn't blame Altera for this. You yourself said "I realize this essentially automatic using Qsys...". Your design choices and/or build methods in not using QSYS are making it harder for you than it needs to be.

I totally blame Altera. To assume all design can be forced into a proprietary system integration tool is a marketing decision. This Altera decision intentionally makes things difficult for engineers that aren't willing to work in the way prescribed by Altera marketing. By the way, I just used the equivalent AXI version of this in the Xilinx build environment. It was easy and worked great. Score one for Xilinx.

I don't get it. All FPGA vendors to my knowledge use proprietary tools. Are you really saving your organization money by avoiding them? Is it a portability question? I'm genuinely confused as to why a designer would want to avoid tools that make design quicker to do.

Windows vs Linux. slick+opaque versus rough+transparent. Different ways of solving the same problem. I use both, depending on the problem.

I am also curious what attribute of your VHDL and build process prevent you from managing the interconnect with Qsys, and also what mechanism Xilinx provides that makes this type of work much easier?

In Xilinx, I can directly instantiate a "AXI crossbar" IP core in my code. This allows me to manual connect my AXI ports to the crossbar.