Single Avalon-MM Master to Muliple Avalon-MM Slaves

I totally blame Altera. To assume all design can be forced into a proprietary system integration tool is a marketing decision. This Altera decision intentionally makes things difficult for engineers that aren't willing to work in the way prescribed by Altera marketing. By the way, I just used the equivalent AXI version of this in the Xilinx build environment. It was easy and worked great. Score one for Xilinx.