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I totally blame Altera. To assume all design can be forced into a proprietary system integration tool is a marketing decision. This Altera decision intentionally makes things difficult for engineers that aren't willing to work in the way prescribed by Altera marketing. By the way, I just used the equivalent AXI version of this in the Xilinx build environment. It was easy and worked great. Score one for Xilinx.
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I fail to see that it would be easier to achieve this with Xilinx's IP Integrator than with Altera's Qsys.
Perhaps you are more acquainted with Xilinx's tools?
The original post is a bit vague to me and it would help to see an actual specimen of one of your VHDL modules you want to integrate.
Honored Contributor
