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Altera_Forum
Honored Contributor
9 years agoIn Xilinx, I can directly instantiate a "AXI crossbar" IP core in my code. This allows me to manual connect my AXI ports to the crossbar.
In Xilinx, I can directly instantiate a "AXI crossbar" IP core in my code. This allows me to manual connect my AXI ports to the crossbar.