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Altera_Forum
Honored Contributor
Honored ContributorSingle Avalon-MM Master to Muliple Avalon-MM Slaves
I'm trying to connect multiple Avalon-MM slaves to a single Avalon-MM Master. I realize this essentially automatic using Qsys, if you're IP is defined as modules in Qsys. But all of my IP is alrea...
Altera_ForumHonored Contributor
Honored ContributorIn Xilinx, I can directly instantiate a "AXI crossbar" IP core in my code. This allows me to manual connect my AXI ports to the crossbar.
