Single Avalon-MM Master to Muliple Avalon-MM Slaves

I am also curious what attribute of your VHDL and build process prevent you from managing the interconnect with Qsys, and also what mechanism Xilinx provides that makes this type of work much easier?

In Qsys, it is possible for you to create a Qsys system where you have manually instantiated the interconnect blocks that Qsys normally generates for you, but this approach would be rather tedious and you'd be well off the beaten path and on your own so to speak. And while you could certainly script it, I'm guessing your time would be better spent scripting _hw.tcl files for your VHDL (automatically generated?) components and just using Qsys.