Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

can you also clarify,

After you changed into the testbench subdirectory, you typed in vsim, this brings up a window which expects you to put in the top level testbench to simulate. You don't mention any designs, you say you type vsim, then do msim_setup.tcl, then ld_debug and run -all.

I typed vsim in Questa or ModelSim, it just expects you to load the top level design.

That being said, I clicked on pci_ed_tb after typing vsim as the testbench file, but still couldn't load the design.

# ** Error (suppressible): (vopt-14408) Intel Starter FPGA Edition recommended capacity is 5000 non-OEM instances. There are 9399 non OEM instances. Expect performance to be severely impacted.

--Please not using starter version

I typed vsim in Questa or ModelSim...

--vsim is the command to launch Questa, not the command used inside Questa

That being said, I clicked on pci_ed_tb after typing vsim as the testbench file

--do vsim at pcie_ed_tb/pcie_ed_tb/sim/mentor

Regards,

Rong

I'm not able to upload an example for you to try because the zipped file is still too large. Splitting zip files can't be uploaded.

Regards,

Rong

I think I'm narrowing down what the problem is.

First I wanted to correct you, you stipulated

"--Please not using starter version"

The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed.

Here is what I think the problem is. The top level design module is outside the directory structure that the manual says to change into.

In my design, when I go to C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim

the top level module is there, called pcie_ed_tb.v

This file is nowhere else in the file structure except there.

So when I change to the testbench directory C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor

and type in do msim_setup.tcl it seems to not notice this top level module, I can't find this file anywhere in the Library window.

Can you confirm?

So by doing ld_debug at this point is going to be fatal error if it can't load the top level module. I even put the top level module in the testbench directory and it still won't load it.

The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed.

--On 7/17 we have aligned to AVMM PCIe IP, you're now discussing AVMM+ PCIe IP? My discussion with you so far is all based on the sim of AVMM PCIe IP.

--"No license requirement" in AVMM+ PCIe UG means this IP is free to use, and you can compile the design to get sof. Doesn't mean the Questa starter edition can handle such complicated simulation.

Regards,

Rong

I updated my simulator from the ModelSim Starter Ed and Questa Starter to Siemens Questa, Questa Intel FPGA Ed-64 2024.3 and ran all the previous commands as outlined in the User Guide and I am still getting the "failed to load design" after generating 3000+ errors as previously I got. This leads me to believe there is something I'm not checking in the IP variant checkboxes. I contend, everything was followed according to the User Guide.

Can you please upload your complete folder including the IP variant for my device you generated and upload it to FileTransfer.io or SendGB, which is a free hosting site for files up to 5GB ? Once I receive this, and find out where my errors orginiated from and after sucessful simulation, I'll mark this as Solved and explain what I did wrong.

Sorry I can't use those external links. Due to the limitation of forum, my suggestion is to contact your local DFAE. They could help check your system on-site and provide corresponding supports.

Regards,

Rong

Can you kinly provide your .IP variation file used to simulate the PCI Express core?

And what version of Quartus Pro are you using?

Sure. I'm using Q23.4.0 Pro.

Extract the .zip to get .ip

Regards,

Rong

Hi,

I finally find a way to upload the generated project. Please extract below files individually:

s10_ed.zip.zip --> s10_ed.zip

s10_ed.z01.zip --> s10_ed.z01

s10_ed.z02.zip --> s10_ed.z02

s10_ed.z03.zip --> s10_ed.z03

s10_ed.z04.zip --> s10_ed.z04

Put s10_ed.zip, s10_ed.z01, s10_ed.z02, s10_ed.z03, s10_ed.z04 into the same directory(e.g. ss) then extract s10_ed.zip to another directory(e.g. ../st). All .z0X files will be merged into one file called pcie_s10_hip_avmm_bridge_0_example_design_gen3x8dma_original.zip.

Hope this helps.

Regards,

Rong