Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I think I'm narrowing down what the problem is.

First I wanted to correct you, you stipulated

"--Please not using starter version"

The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed.

Here is what I think the problem is. The top level design module is outside the directory structure that the manual says to change into.

In my design, when I go to C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim

the top level module is there, called pcie_ed_tb.v

This file is nowhere else in the file structure except there.

So when I change to the testbench directory C:\intelFPGA_pro\23.3\avmm_bridge_512_0_example_design\pcie_ed_tb\pcie_ed_tb\sim\mentor

and type in do msim_setup.tcl it seems to not notice this top level module, I can't find this file anywhere in the Library window.

Can you confirm?

So by doing ld_debug at this point is going to be fatal error if it can't load the top level module. I even put the top level module in the testbench directory and it still won't load it.