Forum Discussion

RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago


# ** Error (suppressible): (vopt-14408) Intel Starter FPGA Edition recommended capacity is 5000 non-OEM instances. There are 9399 non OEM instances. Expect performance to be severely impacted.

--Please not using starter version


I typed vsim in Questa or ModelSim...

--vsim is the command to launch Questa, not the command used inside Questa


That being said, I clicked on pci_ed_tb after typing vsim as the testbench file

--do vsim at pcie_ed_tb/pcie_ed_tb/sim/mentor


Regards,

Rong