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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

can you also clarify,

After you changed into the testbench subdirectory, you typed in vsim, this brings up a window which expects you to put in the top level testbench to simulate. You don't mention any designs, you say you type vsim, then do msim_setup.tcl, then ld_debug and run -all.

I typed vsim in Questa or ModelSim, it just expects you to load the top level design.

That being said, I clicked on pci_ed_tb after typing vsim as the testbench file, but still couldn't load the design.