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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

Hi,

I finally find a way to upload the generated project. Please extract below files individually:

s10_ed.zip.zip --> s10_ed.zip

s10_ed.z01.zip --> s10_ed.z01

s10_ed.z02.zip --> s10_ed.z02

s10_ed.z03.zip --> s10_ed.z03

s10_ed.z04.zip --> s10_ed.z04

Put s10_ed.zip, s10_ed.z01, s10_ed.z02, s10_ed.z03, s10_ed.z04 into the same directory(e.g. ss) then extract s10_ed.zip to another directory(e.g. ../st). All .z0X files will be merged into one file called pcie_s10_hip_avmm_bridge_0_example_design_gen3x8dma_original.zip.

Hope this helps.

Regards,

Rong