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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

The User Guide specifically mentions "No license is required", therefore it is free of cost to simulate including using the starter ed.

--On 7/17 we have aligned to AVMM PCIe IP, you're now discussing AVMM+ PCIe IP? My discussion with you so far is all based on the sim of AVMM PCIe IP.

--"No license requirement" in AVMM+ PCIe UG means this IP is free to use, and you can compile the design to get sof. Doesn't mean the Questa starter edition can handle such complicated simulation.



Regards,

Rong