my PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core

"pll_powerdown"? What FPGA are you using? Do you mean the reset port - 'rst'?

What is your clock source? Is it a good clock source with low jitter? What frequency are you trying to lock to?

Cheers,

Alex

Arria 10GX. FPLL have input pin - "pll_powerdown". This is analog of reset

Input clock 50MHz, output clock -156.25MHz. Higher lickly jitter is high

What are you connecting pll_powerdown to? Are you using it with a Transceiver and is it connected to that? Is it connected to the correct reset controller?

The user guide states it "needs to be connected to a dynamically controlled signal". Don't expect it to work if you're driving it directly.

Cheers,

Alex

When I tested my project, then through the reset controller I changed the status pll_powerdown, but pll_locked did not change its state. Null.

Are you simulating this? pll_powerdown doesn't behave correctly in simulation.

If you're on hardware then it could be that your 50MHz clock source isn't good enough. What is this clock source and is it clean with low jitter? Is this on a development board or your own hardware?

Cheers,

Alex

Well-well, in my project "pll_powerdown" is not connected inside fpll, but I made change to*.qsf-file (set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"), pll_powerdown is connected and "pll_locked" is OK!

Please do not connect this pin through qsf file , connect through the IP .( Attaching the screen shot for your reference)