ДлазаNew Contributor6 years agomy PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core
Recent DiscussionsCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsCyclone V CAN triple samplingSolvedR_Tile PCIEAgilex 7 I F-Tile Direct PHY: example TB doesn't workSolvedWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?
New ContributorNew Contributor
Frequent ContributorFrequent ContributorNew ContributorFrequent Contributor
