ДлазаNew Contributor6 years agomy PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core
ДлазаNew Contributor6 years agoArria 10GX. FPLL have input pin - "pll_powerdown". This is analog of reset
Recent DiscussionsIntroducing the Altera Community AI Responder — BetaRequest about FPGA 10CL025YU256A7GSolvedAgilex5 o_tx_ready and o_rx_ready not asserting[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration processMT25QL128 Not Available in ALTASMI_PARALLEL Configuration Device List
