my PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core

Well-well, in my project "pll_powerdown" is not connected inside fpll, but I made change to*.qsf-file (set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"), pll_powerdown is connected and "pll_locked" is OK!