my PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core

Are you simulating this? pll_powerdown doesn't behave correctly in simulation.

If you're on hardware then it could be that your 50MHz clock source isn't good enough. What is this clock source and is it clean with low jitter? Is this on a development board or your own hardware?

Cheers,

Alex