my PLL does not set "pll_locked" to 1 when I lower "pll_powerdown" to 0. The flag "PLL Auto Reset" is set in the IP core

"pll_powerdown"? What FPGA are you using? Do you mean the reset port - 'rst'?

What is your clock source? Is it a good clock source with low jitter? What frequency are you trying to lock to?

Cheers,

Alex