Occasional ContributorLVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)
I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in order for me to be able move forward with the design.
The LVDS SERDES IP settings are as follows:
General Settings:
-----------------
Functional mode: RX DPA-FIFO
Number of channels: 16
Data rate: 1352 Mbps
SERDES factor: 8
PLL Settings:
-------------
Desired inclock frequency: 676 MHz
Receiver Settings:
Enable rx_dpa_reset port: checked
Enable rx_fifo_reset port: checked
Clock Resource Summary:
-----------------------
Fast clock: 1352 MHz
Load enable: 169 MHz
Core clock: 169 MHz
So on the SERDES output side I have 128-bit wide data running at 169 MHz.
The user guide recommended initialization sequence is:
1. Assert PLL and DPA reset
2. Deassert PLL reset and monitor PLL lock
3. When PLL lock is stable, deassert DPA reset
4. Let DPA use training pattern to lock
5. When DPA lock asserts, assert FIFO reset for at least one parallel clock cycle
6. Deassert FIFO reset
I am following the recommendation and when building the FPGA end up with recovery timing violations from the DPA lock flop to the serdes DPA FIFO.
These are the details on how I am generating the resets:
rst_n - external low active reset input pin
serdesPllLocked - PLL lock out of the SERDES block
clk_169 - rx core clock output of the SERDES block
serdesDpaReset - DPA reset input to the SERDES block
reset_n_169 - reset for the 169 MHz clock domain logic
serdesFifoReset - DPA FIFO reset input to the SERDES block
//Reset logic
assign reset_n_int = rst_n & serdesPllLocked;
always @(posedge clk_169 or negedge reset_n_int) begin
if (reset_n_int == 1'b0) begin
serdesDpaReset <= 16'hFFFF; // DPA reset assert
reset_n_169 <= 1'b0;
end
else begin
serdesDpaReset <= 16'h0000; // DPA reset deassert
reset_n_169 <= 1'b1;
end
end
// reset ALL DPA FIFOs if ANY of the DPAs are not locked
assign serdesFifoReset = {16{(~&serdesDpaLock)}};
Attached is the timing report of one of the failing paths.
Is there something I am doing specifically wrong, or does anyone have recommendations on how to fix the timing violations?
Thank you so much!
