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Occasional Contributor

5 years ago

LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...

violation_rpt.txt16 KB

KennyT_altera

Super Contributor

5 years ago

Hi,

Thanks for attaching the design.

I look into the recovery failure, it is internal of the LVDS module. Can you try the recommendation mention in

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

page 25

Sorry that Rahul provide a wrong assumption that inside the IP will not have the timing violation. This is untrue especially for LVDS.

Thanks,

Best regards,

Kenny Tan

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LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

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