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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

LVDS Serdes DPA FIFO reset recovery timing violation issue (Cyclone 10 GX)

I am trying to deserialize a 16 bit wide DDR data input running at 676 MHz using an LVDS SERDES IP and get recovery timing violations on the DPA FIFO resets. I am looking for help on fixing those in ...
designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

I am not sure I understand the reply. Would you mind describing the problem a bit further? Also, do you have a suggested change to fix the problem?

Thanks!